The Chip Industry Agrees to Change a Forty-Year-Old Standard

The photomask is the stencil through which a chip's pattern is projected onto silicon. For roughly forty years it has been six inches square. On 8 September 2026 the four companies that define the leading edge of semiconductor manufacturing agreed, in public, to change that, because the optics of the newest lithography machines have made the old size a bottleneck for the largest AI chips.

Why the mask has to grow

ASML's High-NA EUV scanners use anamorphic optics with different demagnification in each axis, which halves the exposure field compared with standard EUV. A die that once fitted in one exposure now needs two, stitched together. Reuters notes that current EUV tools print dies up to about 800 square millimetres, a limit that Nvidia and Google accelerators already reach. Stitching works, but it costs throughput: Intel's SPIE presentation data, as reported by Tech Times, puts the penalty at roughly 30% of scanner output.

A larger mask restores the full field. The initiative, formed by ASML and TSMC on 7 September ahead of the SPIE Photomask Technology conference and announced the next day, targets a 12-inch mask pilot line by 2031 and full lithography system readiness for advanced-node production by 2033. In the meantime, the release states, High-NA will be adopted for production using current 6-inch masks, and TSMC intends to use ASML's High-NA technology in high-volume manufacturing for advanced nodes starting in 2030.

Who signed on, and what each said

Samsung Electronics said it joined the 12-inch initiative on 8 September and plans to put High-NA EUV into DRAM high-volume manufacturing by 2028, which it describes as an industry first. Intel Foundry, which said on 7 September that it has processed more than one million wafers on High-NA, is focused on near-term enablement on 6-inch masks with or without stitching and on the transition to 6-by-12-inch masks; it has worked on the larger format with ASML, mask makers and suppliers for more than three years. SK Hynix told Reuters it is evaluating participating and targets 2028 for High-NA in DRAM mass production.

Reuters also drew the current state of play: High-NA tools are used for production at Intel but not yet for high-volume work at TSMC or Samsung. ASML CTO Marco Pieters told Reuters: 'If we're going to pull it off as an industry, then you'll actually see that the productivity of those systems will go up by 40%.' TSMC chairman and chief executive C.C. Wei, in the joint release, said the industry unlocks possibilities 'that no single company could achieve alone'.

What changes

For chip designers, the promise is a return to single-exposure dies at the largest sizes, with the throughput and yield economics that implies. For the mask ecosystem, it is a decade of new tooling: blanks, writers, inspection and pellicles all sized for a format that does not exist in volume today. For the AI industry, it is a signal about the length of the current build-out. Nobody aligns on a 2033 production target for a cycle they expect to end in 2028.

Who benefits, who is at risk

Beneficiaries: ASML, which sells the scanners either way; mask-equipment makers with a new format to supply; and accelerator designers who get bigger reticles. At risk: suppliers built around the 6-inch standard who cannot fund the transition, and anyone assuming High-NA economics will improve before the early 2030s.